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NI Instruction Sequencer IP by NI - Toolkit for LabVIEW Download

This IP contains a memory to hold sets of instructions, called sequences, which can be issued from the IP on the FPGA to another component on the FPGA, such as a digital protocol generator. This facilitates FPGA-based reconfiguration.

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ReleasedMay 19, 2016
Publisher NI
License NI Sample Code License
LabVIEW VersionLabVIEW>=13.0
Operating System Windows
Project links


This IP contains a memory to hold sets of U32 data values, or instructions. Instructions are grouped into sequences, and there may be one or more sequences in the memory. Events on the FPGA cause an entire sequence of instructions to be sent to the downstream IP, accommodating back-pressure or flow control. After a sequence is generated, the IP advances to the next sequence in the memory. Once all sequences have been generated, the IP returns to the first sequence, enabling looping.

Release Notes (May 19, 2016) no release notes for this version

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