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NI SPI IP by NI - Toolkit for LabVIEW Download

This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality.

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ReleasedMay 19, 2016
Publisher NI
License NI Sample Code License
LabVIEW VersionLabVIEW>=13.0
Operating System Windows
Project links Homepage  


This VI must be placed in a single-cycle timed loop for guaranteed behavior.

Serial Peripheral Interface (SPI) buses are commonly used to communicate between a controller (master) device and a target (slave) device. In general, SPI buses require four lines for communication: chip select/clock enable, serial clock, master serial data out (MOSI), and master serial data in (MISO). In some cases only a subset of these lines are used; some devices multiplex both MOSI and MISO onto a single bidirectional data line. This IP includes LabVIEW FPGA code for both an SPI master and an SPI slave.

Release Notes (May 19, 2016)

Adds examples for CompactRIO and R Series simulation. FPGA IP is unchanged.

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